Heterolithic microwave integrated circuits (HMIC) are one viable approach to low cost mass produced integrated circuits for rf and microwave applications. To this end, the use of the heterolithic structure in which silicon pedestals are selectively disposed about various materials to include glass for fabrication of integrated circuits, has been employed in a variety of applications. Examples of such integrated circuits and the processes for the manufacture thereof are as found in U.S. Pat. Nos. 5,268,310 and 5,343,070 to Goodrich et al., the disclosures of which are specifically incorporated herein by reference. In such an integrated circuit, what is generally required is the ability to make series connections and elements on the top surface isolated from connections on the bottom surface. Additionally, the ability to make required connections from the top surface of the integrated circuit to the bottom surface is desired.
The interconnections from devices on the top surface to the bottom surface on which is disposed the ground plane of the HMIC are relatively straight forward. These interconnections are generally effected by the use of heavily doped silicon pedestals for conduction of current from the top surface to the bottom surface of the IC. Conversely, in order to effect the series connections and elements on the top surface, the silicon pedestals are connected to elements on the top surface of the HMIC, but are isolated from the ground plane. In order to achieve this isolation, an insulating material such as polyimide is disposed between the pedestal and the ground plane to act as an isolator between the top surface and the bottom surface so as to electrically isolate selected portions of the top surface from the bottom surface.
FIG. 1 shows the final result of the prior technique of manufacture for the HMIC. The general structure having the silicon pedestals 101 having the glass material 102 for selective isolation of the various pedestals from one another is a relatively standard structure as is described in the above referenced patent application and patent. In the process of fabricating the structure shown in FIG. 1, those pedestals 103 which are effectively isolated from the lower surface of the substrate, a metal layer 104, are effected as follows. After the formation of a pedestal such as that shown at 101, the undersurface or backsurface of the wafer is selectively etched in order to backfill the etched portion with an electrically nonconductive material such as polyimide 105. Thereafter, the metal layer 104 is deposited through standard technique and the selected isolation of elements 106 from the metal ground plane 104 in order to effect the desired interconnections on the top surface of the substrate is achieved.
One of the critical factors in the use of the heterolithic structure as is shown in FIG. 1 is the overall thickness of the integrated circuit. To this end, the thickness of the glass used as the dielectric dictates the inductance of various elements on the top side of the substrate. The various elements, such as inductors, that are used in the rf circuit on the top surface of the substrate must be properly impedance matched and in fact may be part of the matching circuit. Accordingly, the elements such as inductors, which form resonators in a matching circuit, must have a resonant condition at a prescribed frequency in order to properly effect the impedance matching of the various elements. Because the thickness of the substrate dictates the inductance of various resonant elements, it is clear that the precision of the resonant circuit elements on the top surface of the substrate is dependent upon the precision of the thickness of the substrate. Accordingly, in the processing of heterolithic microwave integrated circuits, the thickness of the dielectric between the top surface circuit element and signal lines and the ground plane of the HMIC must be maintained to a very precise value.
In order to properly effect the desired thickness of the dielectric and the isolation of certain elements as shown in FIG. 1, the wafer is processed with the precision of the thickness in mind. To this end, the process of bonding the glass to the silicon through standard fusion techniques as is described in the above referenced patents is effected. Thereafter, the silicon pedestals are etched through the back of the wafer after the final thickness of 5 to 8 mils is achieved. Accordingly, cavities are formed and these cavities must be filled with an electrically nonconductive material in order to properly isolate the selected silicon pedestals from the metal ground plane which is deposited as shown at 104. It is clear that the desired thickness is maintained and thereby the performance characteristics of the various elements and the required impedance matching is carried out with great precision.
Unfortunately, the process fabricating the HMIC with the vias as well as pedestals isolated from the ground plane as is shown in FIG. 1 has proved to be very problematic. The problems encountered in processing the wafer generally are direct results of attempts to process wafers which have been etched to be too thin. Often this is manifest in breakage, as well as incomplete electrical isolation of the series elements. The latter is difficult to inspect after fabrication. The resulting yields are unfortunately very unpredictable ranging from 0% to a maximum of on the order of 68%. Even if it were possible to consistently achieve the yields of 68%, this is an unacceptable value if one is to maintain low cost as is required in the rf and microwave wireless markets.
Accordingly, what is needed is a new process for fabricating heterolithic microwave integrated circuits which affords the precision of thickness of the dielectric between the top surface and the ground plane, thereby enabling good performance characteristics of the resulting circuit while increasing the manufacture yields to an acceptable and consistent level. To this end, a technique is required for fabricating HMIC circuits having selectively isolated pedestals for series elements and circuits as well as vias for interconnecting the top surface of the HMIC to the lower surface ground plane. By increasing the manufacturing yields to an acceptable level, the overall cost of the end product will be reduced without sacrificing the performance of the circuit.